This invention relates to a semiconductor device having System-In-Package (SIP) structure.
The semiconductor device of the SIP structure is formed by sealing a plurality of semiconductor chips in a single package to form an integrated system. The semiconductor device of the SIP structure has advantages of low electric power consumption, high performance, and small mounting area.
Particularly, there is known a semiconductor device called as Wafer-Level SIP, which is formed by sealing the semiconductor chips on a wafer and separating the wafer into individual semiconductor devices.
For example, there is known a semiconductor device of the SIP structure in which a second semiconductor chip is laminated on a first semiconductor chip, and a protection film (thicker than the second semiconductor chip) is formed on the first semiconductor chip. The protection film has a hole (having the same size as the second semiconductor chip) in which the second semiconductor chip is mounted.
Such a semiconductor deice has a wiring layer connected to the first and second semiconductor chips, and electrode posts connected to the wiring layer. The top surfaces of the electrode posts are exposed at the surface of a sealing resin layer covering the surface of the semiconductor chips. Solder balls are connected to the top surfaces of the electrode posts (see Japanese Laid-Open Patent Publication No. 2001-257310: referred to as Patent Publication 1).
Further, in order to increase the interval between electrode terminals, there is known a semiconductor device including a base frame (made of, for example, an organic material) having an opening portion, and a semiconductor chip mounted therein having a plurality of electrode pads. Such a semiconductor device includes wiring patterns running from the electrode pads of the semiconductor device to the surface of the base frame, and electrode terminals formed on the wiring patterns at the surface of the substrate (see Japanese Laid-Open Patent Publication No. 2004-165190: referred to as Patent Publication 2).
Furthermore, in order to increase the interval between electrode terminals, there is known a semiconductor device having an extension portion (made of, for example, a resin) that contacts and surrounds the side surfaces of the semiconductor chip. Above the extension portion, electrode terminals are formed on the wiring patterns running from the electrode pads of the semiconductor chip (see Japanese Laid-Open Patent Publication No. 2004-165192: referred to as Patent Publication 3).
Moreover, there is known a semiconductor device having an insulating extension portion (made of, for example, a resin) that contacts and surrounds the side surfaces of the semiconductor chip. Above the extension portion, electrode terminals are formed on the wiring patterns running from the electrode pads of the semiconductor chip (see Japanese Laid-Open Patent Publication No. 2004-165194: referred to as Patent Publication 4).
However, in the semiconductor device disclosed in Patent Publication 1 having laminated semiconductor chips, the heat generated by the respective semiconductor chips is not well dissipated, and therefore the heat may adversely affects the operation of the semiconductor chips or the like.
Further, in the semiconductor devices disclosed in Patent Publications 2, 3 and 4, the semiconductor chips are surrounded by the base frame (Patent Publication 2) or the extension portion (Patent Publications 3 and 4) made of, for example, resin or organic material, and therefore the heat dissipation of the semiconductor chips may be reduced, so that the high-frequency characteristics may be adversely affected.
Accordingly, there is a demand for a semiconductor device capable of providing higher performance of a package, enhancing heat dissipation and high-frequency characteristics, and enhancing the stability in operation.